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Neural Foundry's avatar

The EUV lithography constraint extends all the way to memory manufacturng. HBM stacks need the tightest process nodes for their logic die componenets. SK Hynix and Samsung both rely on ASML's tools to push density in those layers. Its fascinating how one company controls such a crtiical chokepoint.

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Rainbow Roxy's avatar

Thanks for writing this, it clarifies a lot. I wonder if this bottleneck was touched on in your earlier peice about global chip infrastructure?

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